High-resolution digital generator of graphic symbols with edging

ABSTRACT

A graphic symbol, completely digital, video signal generator, suitable for use in a television broadcast display control system, derives high resolution (50 nanosecond video dot period) symbols with edging employing off-the-shelf low resolution (200 nanosecond period) shift registers. This is accomplished by employing four different phase clocks each having a low repetition rate (5 MHz). Separate independent edge key and monochrome video signals are derived as the symbol video output of the generator.

[ Nov. 4, 1975 3,725,723 4/1973 Colston e1 340/324 AD $786,478 l/l974340/324 AD 3 786,48l l/I974 Hartman.i.i.u,......,....i.i 340/324 AD1812,491 5/l974 Barrzlclough et 340/324 AD Primary ExaminerDavid L.Trafton Attorney, Agent, or Fz'rmEdward J. Norton; George J. Seligsohn[57] ABSTRACT A graphic symbol, completely digital, video signalgenerator, suitable for use in a television broadcast display controlsystem, derives high resolution (50 nanosecond video dot period) symbolswith edging employing otf-the-shelf low resolution (200 nanosecondperiod) shift registers. This is accomplished by employing fourdifferent phase clocks each having a low repeti- GENERATOR OF GRAPHICSYMBOLS WITH EDGING Inventor: Robert John Clark, Dorion, CanadaAssignee: RCA Corporation, New York, NY.

Filed: Nov. 7, 1974 Appl. No: 521,784

US. Cl. 340/324 AI); 178/75 D Int. G06F 3/14 Field of SearchWHW. 340/324AD; 178/745 D,

l78/DIG. 22

References Cited UNITED STATES PATENTS United States Patent Clark IHIGH-RESOLUTION DIGITAL Y o y e S g e e 4 ii 252 s A. m m d mwmm m5:Sumo c .HH M "n e e m 65 $523 5 m a we m .w r a 25 F0 m P am 2 e m we 4an mmu u A500 w H e; ra pm fi e 0 m m i d e l n u u l l| i i .m m m We52 m a s w v C m h m m 35; 4r M m m m m 165 a 22 Km iv E D VMMW e i we 9i ysr any e mm mm D s l C a m i 25% m mvwm m an H .n\. f oronx 2 ill r WA o a 533 4 2 E H m t O 6 26 5 2E 52; h 0 Q 4 M l 2 M 0 w 6 m 4 4 0 m 5w 5 r m m r23 m o s m -9% w w w N c o 0 25m w w 4 e m o c was 58 m 0 nor 9 2222 r m w A m G 25 W n l P 4 ECU rlllrlll 2 I o m o m 5 Li F E E o0 0 0 A a c 0 A m Q m flab HT MEMM 000m 0000 Q wwww m M M D no l l V W WW V W V W M w E N D D D D D L BM Q A A A A A l mm L 4 4 4 4 4 0 P .HOE 04 n n n n w w wmm o m o m w mwww o s m 4 4 4 4 4 A 3 3 3 1 3 TNEE l. H Hm mmw 6 B m w. sstc m ws U o w m A mM m 0 L H S RNFEP 4 h m wS DEM m I W4 WWW. H H a I, H Cr n r t a n om nn t a m a t m e t e WEE n e k TT TLARM 8 m mm so WW mmwmw Mmr mmm m m mw mm D S S W D M0 Wm AR 1) D0 5 l 22 2 6 7 7 7 7 D 9 9 9 9 9 R 0 H HHHH 0 m 0 5 4 3 7 7 NNK B 4 A v N w E0%? K 8 9 Z 7 6 5 O 8 7 9 7 3 .2 2 3 O0 00 O u 8 7 4 7 00 b 3 3 3 3 3U.S. Patent Nov. 4, 1975 Sheet 1 GT5 3,918,039

HDRIVE: L IFE O /l00 PRIOR ART SIGNAL T SOURCE IZBEQ v DRIvE H2 IGRAPHIC COMPOSITE SYMBOL vIDEo DIGITAL SIGNAL TO VIDE SYMBOL DERIVATIONTRANSMITTER SIGNAL GEN vIDEO MEANS COMPOSITE VIDEO /II4 SYMBOL ll0 /||8DISPLAY a TIMING AND COLOR IGOLOR CONTROL MEANS CONTROL TELEVISIONBROADCAST DISPLAY CONTROL SYSTEM 6 BIT 9 BIT CHARACTER SYMBOL GENERATORADDRESS STORES 64 CODE SYMBOLS (8x a MATRIX) I GENERATOR MEMORY 200 3BIT Tv LINE A BIT DOT PATTERN CODE 204 CODE TV SYNC SYMBOL LOAD DOTPULSE 2 2? TV BLANK I O REGISTER SERIAL vIDEO OUT PULSE OUTPUT DOT CLOCKPULSESEA 202 vIDE0 MIXER/AMP LOW RESOLUTION PRIOR A RT CHARACTERGENERATOR U.S. Patent Nov. 4, 1975 Sheet 2 of5 3,918,039

6 EBT SYM L STORES e4 CODE 300 SYMBOLS ADDRESS CHARACTER (32 32 MATRIX)/6'. 34

GENERATOR MEMORY 5 BIT TV LINE /52 BIT DOT PATTERN CODE 306 CODE 32 BMTv SYNC 304 SEER/5% SYMBOL LOAD DOT PULSE SHIFT TV BLANK DELAY ARREGISTER SERIAL VIDEO LINES PULSE OUTPUT DOT CLOCK PULSES 302 HIGHRESOLUTION RM Affl CHARACTER GENERATOR WITH SYMBOL EDGING DEVICE 5 T 32x 32 MATRIX MATRIX SYMBOLS SYMBOLS F/G'. 2B F/G. 3L9

2(50 ec) DOTS (minim uni) i 2 TV LINES PER FRAME (minimum) H6. 30

MONOCHROME EDGE KEY VIDEO VIDEO US. Patent Nov. 4, 1975 Sheet 4 of53,918,039

CLOCK TIMING so NANOSECONDS 5o NANOSECONDS TTI IT- DOT CLOCK l I I PHASEA CLOCK f I FL ['1 Fl I- PHASE B CLOCK FL FL ['1 F] H PHASE 0 CLOCK I LT1 I I FI I I PHASE 0 CLOCK I' I I L I I I L I I VIDEO SHIFT REGISTERLOAD TIMING SYMBOL DISPLAY SYMBOL I SYMBOL 2 SP E 32 pu sEs 32 PULSES-PHASE A CLOCK JUL--- LOAD DOTS PULSE I' I US. Patent Nov. 4, 1975 Sheet5 of5 3,918,039

PHASEA CLOCK Fl FL FL PHASE B CLOCK n n n PHASE 0 CLOCK Fl Fl FL PHASE 0CLOCK 1 1 L VIDEO A DOT PULSE l 1 vmeo A DOT PULSE FL VIDEO AI 0R A2 DOTPULSE J L VlDEO Al' 0R A2 DOT PULSE L VIDEO B DOT PULSE l l VIDEO B DOTPULSE VIDEO Bl 0R B2 DOT PULSE l" l VIDEO Bl 0R B2 DOT PULSE l VIDEO (2DOT PULSE I' L VIDEO (2' DOT PULSE Fl VIDEO Cl 0R c2 DOT PULSE VIDEO clOR 02' DOT PULSE 1 VIDEO D DOT PULSE I l VIDEO 0' DOT PULSE FL VIDEO 0|0R D2 DOT PULSE J l VIDEO 0| OR 02' DOT PULSE FL TIMING DIAGRAM-VlDEOOUTPUT PULSES F/6. 6

HIGH-RESOLUTION DIGITAL GENERATOR OF GRAPHIC SYMBOLS WITH EDGING Thisinvention relates to the digital generation of video signals manifestingcharacters or other graphic symbols and, more particularly, the digitalgeneration, in a manner suitable for television broadcasting, of videosignals manifesting high resolution graphic symbols with edging.

For many purposes, such as in a conventional video terminal, the displayon a television monitor of relatively low resolution graphic symbolswithout edging is perfectly acceptable. By way of example, in most videoterminals, each symbol is composed of a dot matrix of only 5 X7 dots.While this resolution is sufficient to provide intelligibility of adisplayed message composed of such character symbols, it is insufficientto meet the high resolution requirements of broadcast television. Toprovide the high resolution which is most desirable in broadcasttelevision, each character or other graphic symbol should be composed ofa much larger dot matrix, such as a 32 X32 dot matrix for example.

The clock rate, (in the order of 5 MHZ) required for the digitalgeneration of low resolution graphic symbols without edging (such asemployed in conventional video terminals) is compatible with theswitching speeds of standardly available shift registers and the otherstandard elements of video-signal digital generators. Further, 5 MHz iscompatible with the video passbands of television monitors and standardtelevision sets. However, the clock rate (in the order of MHZ) requiredfor the digital generation of high resolution graphic symbols withedging is higher than the switching rates of standard shift registersand the other standard elements of a digital generator of highresolution graphic symbols with edging. In addition, a 20 MHz clock rateprovides a dot duration of only 50 nanoseconds which, due to the videobandwidth and response time of a standard television set, is much belowthe approximately 150 nanosecond minimum required to maintain symbolbrightness in both black-and-white and color television sets, and iseven further below the minimum of approximately 200 nanoseconds requiredto obtain satisfactory symbol color saturation in color television sets.For these reasons. in the past, generators of high resolution graphicsymbols with edging for use in television broadcasting were notcompletely digital in construction, but required expensive analogelements which were capable of operating effectively at a high clockrate (in the order of 20 MHZ).

In accordance with the principles of the present invention, there isdisclosed and claimed a completely digital generator of high resolutiongraphic symbols with edging. This is accomplished by providing fourphasetelevision video signals, each at a relatively low clock rate and thenusing these four-phase TV video signals for deriving the requiredhigh-clock rate output video signals from the digital generators.

These and other features of the present invention will become moreapparent from the following detailed de scription taken together withthe accompanying drawing, in which:

FIG. I is a block diagram of a typical prior art television broadcastdisplay control system, of a type which provides the display of graphicsymbols.

FIG. 2a is a block diagram of a typical low resolution prior art digitalcharacter generator, and FIG. 2b illus- 2 trates a typical lowresolution character generated by the generator of the type shown inFIG. 2a;

FIG. 3a is a block diagram ofa typical high resolution prior artcharacter generator with a symbol edging device. FIG. 3b is a dot matrixof a high resolution charac ter without edging, and FIG. 30 shows atypical high resolution character with edging;

FIG. 4 is a block diagram of a graphic symbol digital video signalgenerator embodying the present invention;

FIG. 5 is a timing diagram of the clock and load pulses employed in FIG.4, and

FIG. 6 is a timing diagram of the video output pulses derived by thevideo signal generator of FIG. 4.

Referring now to FIG. I, there is shown. in generalized form, atelevision broadcasting display control system of the type whichincludes a graphic symbol digital video signal generator. Specifically,as shown in FIG. 1, picture video signal source applies one or morepicture video signals as one or more inputs to composite video signalderivation means 102 over picture video connection I04. The picturevideo signals may be generated locally from one or more televisioncameras, video recorders, etc. or. as in the case ofa network program,one or more of the picture video signals may originate at a distantpoint. In any case, any and all of these picture video signals may beapplied as inputs to composite video signal derivation means I02 overconnection 104 at the same time.

Horizontal drive and vertical drive signals from picture video sourceI00 are applied over respective connections I06 and 108 as sync inputsto symbol display timing and color control means 110. Symbol displaytiming and color control means 110 applies timing control signals to aplurality of inputs of graphic symbol digital signal generator 112 overtiming control connection I I4. Graphic symbol digital video signalgenerator 112 applies one or more symbol video signals as an input tocomposite video signal derivation means 102 over connection 116. If thetelevision broadcast is in color, symbol display timing and colorcontrol means 110 applies color control signals to composite videosignal derivation means 102 over connection 118. Of course, if thetelevision broadcast is to be in black-andwhite. both the color controlportion of 110 and color control connection I18 may be omitted.

As is known in the television broadcast art, each of the blocks I00,102, I10 and 112 may include the various switches and control meanswhich are manually operated to provide the desired picture video, symbolvideo and color control input to composite video deri vation means I02and to provide the desired composite video signal output from compositevideo signal derivation means 102. For instance, as is known in thetelevision broadcast art, composite video signal derivation means I02may include suitable video keyers and mixers for selectively combiningthe video signal input thereto over connection I04 and 116 in anydesired manner to provide the television frame format manifested by thecomposite video signal output therefrom. For example, picture videosignals may be selectively combined to provide a so-called split screen"format, or symbol video signals may be superimposed on top of a picturevideo signal or. in the alternative, a video may be employed to "keyout" from the picture the area in a television frame in which a symbolis located. Thus, a television broadcast display control system providesgreat versatility in forming the composite video signal 3 which actuallyis broadcast by the television transmitter.

Referring now to FIG. 2a, there is shown certain elements of the lowresolution prior art character generator of the type employed in videoterminals. Character generator memory 200 typically stores 64 differentalphanumeric symbols. Each symbol may be stored in a dot matrix havingan overall size of 8X8, of which the symbol itself occupies a 5X7portion. This is exemplified for the symbol R, illustrated in FIG. 2b.It will be noted that the low resolution of 5X7 dots for the symbolitself greatly affects the appearance of diagonal portions of thesymbol.

As shown in FIG. 20, character generator memory 200, which is usually aROM, receives a 9 bit character generator address, which is composed ofa 6 bit symbol code (such as the ASCII code) and a three bit TV scanline code. The 6 bit symbol code defines the particular one of the 64storage symbols, such as the symbol R, to be read out, while the threebit TV scan-line code defines the particular one of the eightconsecutive raster scan lines occupied by a row of characters then beingscanned. In response thereto, character generator memory 200 loadseight-bit shift register 202 (which serves as a paralleI-to-serialconverter) with an appropriate group of eight binary bits. Morespecifically, if the symbol being read out is an R and the TV scan linedesignated by the three bit code is either the first or fourth scanline, the eight bit dot pattern code for the symbol R which loads eightbit shift register 202 is l l l [0000, as shown in FIG. 2b. Similarly,as shown in FIG. 2b, this eight bit dot pattern code for the symbol R is10001000 for each of the second, third and seventh TV scan lines; whilethis eight bit pattern code is ll00000 for the fifth TV scan line and isl00l0000 for the sixth TV scan line. To provide a space between wymbolsoccupying different rows of symbols on the television display, the eightbit dot pattern code for the eighth TV scan line is always 00000000.

Eight-bit shift register 202 is loaded in response to the receipt of aload dot pulse input from an associated timing control means. The loadedeight bit dot pattern code in eight-bit shift register 202 is then readout serially in response to applied dot clock shift pulses. The rate ofthese dot clock pulses is normally in the order of MHz, so that eachsuccessive dot has a duration in the order of 200 nanoseconds, which iswithin the video bandwidth capabilities of standard commercialtelevision sets. As further shown in FIG. 2a, the serial video pulseoutput from eight-bit shift register 202 is added to W horizontal andvertical sync signals and a TV blanking signal in video mixer amplifier204, from which the symbol video output of the character generator isobtained.

For television broadcast purposes, the relatively low resolutionprovided by 5X7 matrix symbols, shown in FIG. 2b, is insufficient.Instead, relatively high resolu tion 32x32 matrix symbols, such as shownin FIG. 3b, are required for broadcast television. In FIG. 3b, the widthof each line of the symbol R still has a duration of 200 nanoseconds, sothat it is within the video bandwidth capabilities of a standardtelevision set. However, as shown in FIG. 3b, the high resolutioncapability is achieved by employing a dot duration for the dot matrix ofonly 50 nanoseconds, so that the 200 nanosecond width of each line ofthe symbol R in FIG. 3b is provided by four consecutive 5O nanoseconddots 4 (rather than a single 200 nanosecond dot as in FIG. 2b).

Furthermore, in the case of broadcast television, it is often desired todisplay a high resolution symbol with edging, in the manner shown forthe symbol E in FIG. 3c. As indicated in FIG. 3c, the minimum width ofthe edging may be only I00 nanoseconds, i.e. 2 consecutive dots of 50nanoseconds each. In the past, in order to provide symbols with edging,such as shown in FIG. 3c, required high resolution character generatorswith an analog symbol edging device of the type shown in FIG. 3a.

Referring now to FIG. 3a, character generator memory 300, which likecharacter generator memory 200 may be ROM, stores each of 64 symbols ina 32x32 dot matrix. Each of the 64 symbols is selected by the binaryaddress of a six-bit symbol code applied as an input to charactergenerator memory 300. Character generator memory 300 is furtheraddressed by a five-bit TV scan line code applied as an input theretofor the purpose of selecting the particular one of the 32 rows of theselected dot matrix in accordance with the particular one of 32consecutive TV scan lines then being scanned. In response thereto,character generator memory 300 derives as an output a 32 bit dot patterncode defining the symbol dot pattern of the selected row for theselected symbol. In response to a load dot pulse applied to 32 bit shiftregister 302, the 32 bit dot pattern code from character generatormemory 300 is loaded in parallel into 32-bit shift register 302. Inresponse to dot clock pulses applied as shift pulses 32-bit shiftregister 302 at a relatively high rate of about 20 MHz, a serial videopulse output is obtained from 32 bit shift register 32. This serialvideo pulse output is added to TV horizontal and vertical sync signalsand a TV blanking signal in mixer 304. Although, as so far described,the high resolution prior art character generator of FIG. 3a is digitalin construction, it requires a more expensive nonstandard shift registercapable of operating at 20 MHz, rather than a relatively inexpensivestandardly available shift register operating at 5 MHz employed in thelow resolution prior art character generator of FIG. 20. Furthermore, ifsymbol edging of the type shown in FIG. 3c is desired, the output frommixer 304 must be passed through an edging device, such as symbol edgerdelay lines 306, to produce the symbol video outputs. Due to the highfrequency (20 MHz) requirement of the final video output stages, symboledging, as shown in FIG. 3c, is perfonned by symbol edger 306 usingexpensive analog circuitry, which includes delay lines.

The present invention, embodied in the graphic symbol digital videosignal generator of FIG. 4, provides a technique for generating highresolution digital symbols with edging, which does not require a 32 bit,20 MHz output shift register and in which it is possible to provide aninexpensive digital (rather than analog) symbol edging usingoff-the-shelf 5 MHz digital shift registers instead of analog circuitryincluding delay lines.

FIG. 4 illustrates an embodiment of graphic symbol digital videogenerator 112 of FIG. 1, which incorporates the present invention. As isconventional in graphic symbol digital video signal generators, there isincluded keyboard 400, data input output control logic 402 and displayrefresh memory 404. Block 400, 402, and 404 cooperate in a manner knownin the art to store in display refresh memory 404 the characters makingup the message to be displayed. Specifically,

each character of the message is manifested by a six-bit word symbolcode. This six-bit word symbol code corresponding to each character inthe message is stored within display refresh memory page 404 at alocation thereof which corresponds to the display position of thatcharacter in the format of the displayed message. as is conventional.

In a manner known in the art, the readout of memory page 404 issynchronized by a display refresh address word timing control signalapplied thereto over connection 114 to read out in sequence the entirestored page of six-bit word symbol codes in synchronism with the rasterscan of each successive television frame.

The six-bit word symbol code output from display refresh memory 404 anda five-bit television scan line code applied from timing controlconnection 114 are applied as inputs to character generator memory 406,which is identical in all respects to character generator memory 300 ofFIG. 3a.

The output from character generator memory 406 consists of a 32-bitparallel dot pattern, each bit of which appears on a separate lead ofconnection 408. In response to a load dot pulse from timing control connection 114, bits 1, S, 9, l3. 17, 21, and 29 of the 32-bit parallel dotpattern carried by the corresponding leads of connection 408 are loadedinto eight-bit phase A shift register 410. In a similar manner, bits 2,6, 10, 14, 18, 22, 26 and 30 are loaded into eight-bit phase B shiftregister 412, bits 3, 7, ll, 15, 19, 23, 27 and 31 are loaded intoeight-bit phase C shift register 414, and bits 4, 8, l2, 16, 20, 26, 28and 32 are loaded into eight-bit phase D shift register 416.

Phase A shift register 410 receives phase A clock pulses from timingcontrol connection 114, which occur at a given relatively slow rate,such as 5 MHz. In a similar manner, phase B shift register 412 receivesphase B clock pulses, phase C shift register 414 receives phase C clockpulses and phase D shift register 416 receives phase D clock pulses.Each of phase B, D and D clock pulses occur at the same relatively slowgiven rate, such as 5 MHz, as the phase A clock pulses. However, asshown in FIG. 5, the respective phase A, phase B, phase C and phase Dclock pulses (which are each 50 nanoseconds in duration) are phasedelayed with respect to each other. Specifically, the leading edge ofphase D clock pulse occurs coincidentally with the lagging edge of thepreceding phase A clock pulse; the leading edge of a phase C clock pulseoccurs coincidentally with the lagging edge of preceding phase C clockpulse; the leading edge of a phase D clock pulse occurs coincidentallywith the lagging edge of the preceding phase C clock pulse and theleading edge of a phase A clock pulse occurs coincidentally with thelagging edge of the preceding phase D clock pulse. Thus, the durationsbetween the leading edges of two successive pulses of the same phase is200 nanoseconds (i.e., the clock pulses occur at a frequency of 5 MHz.).

The respective video A, video B. video C and video D output fromrespective shift register 410, 412, 414, and 416, in response to beingshifted by the respective phase A, B, C and D clock pulses appliedthereto, are applied over connection 418 as respective inputs to videodots shaping and phasing flip flops 420. In addition, the respectivevideo A, video B, video C and video D signals are applied as inputs to 1TV line delay logic 422 (which consists of four shift registers, eachhaving a capacity of 256 bits). Block 422 also receives phase A 6 andphase C clock shift pulses, which operate in a manner to be describedbelow in connection with FIG. 6.

The output from 1 TV line delay logic 422, which consists of videosignals A1, B1, C1 and D1, is applied as second inputs to video dotshaping and phasing flip flops 420 over connection 424, and is alsoapplied as inputs to 1 TV line delay logic 426. Block 426, like block422, comprises four 256 bit shift registers, which have phase A andphase C clocks applied as shift pulses thereto. The function performedby delay logic 426 also will be described below in connection with FIG.6.

The outputs from one TV line delay logic 426, which consists of videosignals A2, B2, C2 and D2, are applied as third inputs to video dotshaping and phasing flip flops 420 over connection 428. Video clotshaping and phasing flip flops 420 also has phase A, B, C and D clocksapplied as inputs thereto. as shown.

Delay logic 422, delay logic 426 and video dot shaping and phasing flipflops 420 cooperate to effectively convert the relatively low resolution(5 MHZ) video signals A, B, C and D appearing at the respective outputsof shift registers 410, 412, 414 and 416 into relatively high resolution(20 MHz) video signals appearing at the output of video dot shaping andphasing flip flops 420. More specifically, referring to the timingdiagram shown in FIG. 6, each video A dot pulse has a duration of 200nanoseconds and has its leading edge in time coincidence with theleading edge of the phase A clock. In video dot shaping and phasing flipflops 420, each video A dot pulse is sampled during the occurrence of aphase-D clock pulse, to provide a 50 nanosecond video A dot pulse whichoccurs in time coincidence with a phase D clock. In a similar manner,each 200 nanosecond video B dot pulse is sampled during the occurrenceof a phase A clock to provide a 50 nanosecond video B dot pulse in timecoincidence with the the phase A clock; each 200 nanosecond video C dotpulse is sampled during the occurrence of a phase B clock to provide a50 nanosecond video C dot pulse in time coincidence with the phase Bclock, and each 200 nanosecond video D dot pulse is sampled during theoccurrence of a phase C clock to provide a 50 nanosecond video D' dotpulse in time coincidence with the phase C clock.

Essentially, one TV line delay logic 422 and one TV line delay logic 426together form a center-tapped delay means which provides an overalldelay of 512 successive shift pulses for each respective one of thevideo A, video B, video C and video D signals loaded into the input of 1TV line delay logic 422. Furthermore, since logic 422 cannot be loadedand shifted at the same time, there is provided a phase delay betweenthe loading of the first stage of the four shift registers of delaylogic 422 and the shifting of both these four shift registers and thecorresponding four shift registers of delay logic 426. Specific ally,both the A and B shift registers of both blocks 422 and 426 are shiftedin response to a phase C clock applied thereto, while both the C and Dshift registers of both block 422 and 426 are shifted in response to aphase A clock applied thereto This is illustrated in the timing diagramof FIG. 6, wherein the leading edge of the video Al, A2, B1, and B2 200nanosecond dot pulses occur in time coincidence with the leading edge ofa phase C clock, although the leading edge of the video A dot pulseitself occurs in time coincidence with the leading edge of the precedingphase A clock and the leading edge of the video B dot pulse itselfoccurs in time coincidence with the preceding phase B clock. In asimilar manner, the leading edge of the C1, C2, D1 and D2 dot pulsesoccur in time coincidence with a phase A clock, although the leadingedge of the video C dot pulse itself occurs in time coincidence with thepreceding phase C clock and the leading edge of the D dot pulse itselfoccurs in time coincidence with the preceding phase D clock.

Thus, the overall delay between the occurrence of an A1 or C1 200nanosecond dot pulse on connection 424 with respect to the occurrence ofthe corresponding video A and video C dot pulses on connection 418 isactually I nanoseconds greater than one TV line delay, while in the caseof the video B1 and video D1 dot pulses this delay is actually 50nanoseconds greater than one TV line delay. In a similar manner, theactual delay of the A2, B2, C2 and D2 video dot pulses on connection 428is either 50 or 100 nanoseconds greater than a two TV line delay withrespect to the corresponding video A, video B, video C and Video D dotpulses applied to connection 418.

Despite the 50 or 100 nanosecond phase delay of the 200 nanosecond videodot pulses appearing on connections 424 and 428 with respect to thecorresponding 200 nanosecond dot pulses appearing on conductor 418, thesampling of these video dot pulses in video dot shaping and phasing flipflops 420 is such that the 50 nanosecond video A1 and A2 dot pulsesoccur in time coincidence with a video A dot pulse, the 50 nanosecondvideo B1 and B2 dot pulses occur in time coincidence with a video 8' dotpulse, the 50 nanosecond video C1 and C2 dot pulses occur in timecoincidence with a video C dot pulse and the 50 nanosecond video D1 andD2 dot pulses occur in time coincidence with a video D dot pulse. Thisis illustrated in the timing diagram of FIG. 6, which shows that the 200nanosecond video A1 or A2 dot pulse, as well as the 200 nanosecond videoA dot pulse, is sampled by a phase D clock; the 200 nanosecond B1 and B2dot pulses, as well as the 200 nanosecond video B dot pulse, is sampledby a phase A clock; the 200 nanosecond video C1 and C2 dot pulses, aswell as the 200 nanosecond video C dot pulse, is sampled by a phase Bclock, and the 200 nanosecond video D1 and D2 dot pulses, as well as the200 nanosecond video D pulses, is sampled by a phase C clock.

As further shown in FIG. 4, all the video A, B, C and D signals areapplied through OR gate 430 as a first input to 2 dot delay logic 436.Similarly, all the video A] B l Cl and D1 signals are applied through ORgate 432 as a second input to 2 dot delay 436 and all of the video A2,video B2, video C2 and video D2 signals are applied through OR gate 434as a third input to 2 dot delay logic 436. In addition, the output fromOR gate 430 represents the V signal (the video signal with no dot delayand no TV line delay). In a similar manner, the output from OR gate 432represents the V signal (the video signal with no dot delay and one TVline delay) and the output from OR gate 434 represents the V signal (thevideo signal with no dot delay and two TV line delay).

2 dot delay logic 436, in response to a 50 nanosecond clock appliedthereto, provides a two dot (100 nanosecond) delay in each of its threeinputs to thereby provide three corresponding outputs represented by theV V and V signals. The three output signals from 2 dot delay logic 436are also applied as inputs to 2 dot delay logic 438, which, in responseto 50 nanosecond clock pulses applied thereto, provides an additionaltwo dot nanosecond) delay. This results in corresponding output signalsrepresented by output V V V appearing at the output of 2 dot delay logic438.

As further shown in FIG. 4, eight of the nine output signals from ORgates 430, 432 and 434 and 2 dot delay logic blocks 436 and 438 areapplied as inputs to OR gate 440. In particular, signals V V V V,,,, V VV and V are applied as inputs to OR gate 440, while the remaining one ofthese nine signals, V is applied as an input to an inverter 444 and asan input to signal mixer 446. Horizontal and vertical TV sync signalsand a TV blanking signal are applied as additional inputs to signalmixer 446.

The output of OR gate 440 is applied as a first input to AND gate 442,while the output from inverter 444, manifesting V is applied as a secondinput to AND gate 442.

The symbol video present on connection 1 16 consists of two separatecomponent video signals. The first of these two separate component videosignals is the edge key video signal which appears at the output fromAND gate 442 and the second of these separate component video signals isthe monochrome video signal which appears at the output of signal mixer446. As shown in FIG. 1, the edge key video signal and the monochromevideo signal, which together form the symbol video output present onconnection 116, are applied as control inputs to composite video signalderivation means 102.

It will be seen that the edge key video signal is derived in response tothe presence of any one or more of the eight signal inputs to OR gate440, if and only if signal V is then absent.

As is known, each frame of a television picture is made up of twointerlaced raster-scan fields. When the video signal A, B, C and Dpresent on connection 418 correspond to the first (top) television scanline of a row of symbols to be displayed during a given rasterscanfield, no signal is present on connection 424 and, hence, output signalV, (along with output signals V and V is absent. Similarly, two TV scanlines after the video A, B, C and D signals corresponding to the last(bottom) television scan line of a row of symbols to be displayed duringa given raster-scan field, video A2, B2, C2 and D2 signals are presenton connection 428, but no video signals are present on either connection418 or connection 424. Therefore, in this case, signals V V and V areapplied to OR gate 440, but signal V is absent. During all intermediatescan lines of a display signal, the V signal is present, except for thefirst two dot periods I00 nanoseconds) of the scan of that symbol, whennone of the output signals V V V V, V nor V is present, and during thelast two dot periods 100 nanoseconds) of the scan of that symbol, whennone of output signals V V V V V nor V is present. Thus, because of thefact that a television frame is made of two interlaced raster-scannedfields, the generation of the edge key video signal corresponds to theedge key video portion of FIG. 3c, while the generation of themonochrome video signal corresponds to the monochrome video portion ofFIG.

The edge key video signal and/or the monochrome video signal componentof the symbol video may be made use of in various ways within compositevideo signal derivation means 102. For instance, the edge key videosignal alone may be used to "key out" the picture video. In this case,the picture video would appear both outside the symbol and within themonochrome" video portion of the symbol. A second example would be to ORtogether the monochrome video signal and the edge key video signal tokey out" the picture video. in this case, the symbols would appear asblack" block symbols within the picture field. However, if themonochrome video signal, besides being combined with the edge key videosignal for keying out" purposes, is also employed to gate in a selectedcolor into the mixed composite video signal, the monochrome videoportion of the symbol will appear in the selected color within a black"edging. Further, the combined edge key video signal and monochrome videosignal, beside being used for key out purposes, may also be used forselecting a second color, In this later case, the monochrome videoportion of the symbol will appear in the first color within an edginghaving the second color. Besides these various examples, other ways ofusing either or both the edge key video signal and the monochrome videosignal may occur to the controller of a television broadcast displaycontrol system. In any case, it is the generation of the separate edgekey video signal and monochrome video signal by the techniques embodiedin generator 112 of FIG. 4, and not the various ways of employing thesetwo components of the symbol video within composite video signalderivation means 102, which forms the novel subject matter of thepresent invention,

What is claimed is:

l. in a digital generator of graphic symbols with edging for display ona display device exhibiting a television raster scan, said generatorbeing of the type which includes a character generator memory responsiveto the application thereto of a first multibit symbol code and a secondmultibit scan line per symbol height code for deriving an m bit paralleldot pattern manifesting a selected scan-line portion of a selectedsymbol to be displayed; the improvement therein comprising:

a. a set of n shift registers each having k stages, wherein both n and kare plural integers and m is equal to the produce of n times k;

b. means for loading said k stages of each ordinal one of said n shiftregisters with the i, n-l-z', 2n+i, m-n+i ordinal ones of said hi bits,where i is the ordinal value of that ordinal one of said n shiftregisters;

c. means for applying as shift pulses to each respective one of said nshift registers a corresponding one of a set of n clocks, each of said nclocks consisting of a series of pulses each having a duration of twhich occur at a repetition frequency substantially equal to 1/11], andeach ordinal one of said set of n clocks being phase delayed by a timeinterval substantially equal to r with respect to the preceding one ofsaid set of n clocks, to thereby produce a set of respective outputs ofsaid n shift registers each pulse of which has a duration substantiallyequal to m,

d. first and second serially connected l television scan line delaylogic means having the set of respective outputs of said n shiftregisters applied as respective inputs to said first line delay logicmeans for producing a first set of corresponding outputs from said firstline delay logic means and a second set of corresponding outputs fromsaid second line delay logic means,

e. video dots shaping and phasing flip flops having said set ofrespective outputs of said n shift registers applied as first inputsthereto, said first set of corresponding outputs applied as secondinputs thereto, said second set of corresponding outputs applied asthird inputs thereto, and said set of n clocks as fourth inputs theretofor sampling all of each separate group of corresponding ones of saidfirst, second and third inputs with a different respective predeterminedone of said set of n clocks, whereby said video dots shaping and phasingflip flops derives first, second and third output dot samplescorresponding respectively to said first, second and third inputsthereto, with each dot sample having a duration t;

f. first and second serially connected dot delay logic means, each ofwhich provides a delay substantially equal to a predetermined integralmultiple oft, said first, second and third output dot samples beingapplied as inputs to said first dot delay logic means for producing afirst set of corresponding outputs from said first dot delay logic meansand a second set of corresponding outputs from said second dot delaylogic means, and

g. output means including first means responsive to the presence of thatgiven particular one of said first set of outputs from said first dotdelay logic corresponding to said second output dot samples for derivinga monochrome video signal, and sec ond means responsive to the absenceof said given particular one of said first set together with thepresence of at least another of said first set, any of said first,second and third output dot samples. or any of said second set ofcorresponding outputs from said second dot delay logic means forderiving an edge key video signal.

2. The generator defined in claim 1, wherein m is 32,

n is four, k is eight, and t is 50 nanoseconds, whereby l/nz is fivemegahertz and nt is 200 nanoseconds.

3. The generator defined in claim 2, wherein said graphic symbols arefor display on a display device exhibiting a television raster scan fora frame consisting of two interlaced raster-scan fields, and whereinsaid predetermined integral multiple of l' is two, whereby each of saidfirst and second dot delay logic means provides a delay of one-hundrednanoseconds.

4. The generator defined in claim l, wherein each of said first andsecond serially connected 1 television scan line delay logic meansincludes a second set of n shift registers individually corresponding toeach of the n shift registers of said first mentioned set, each of saidsecond set of n shift registers having a given number of stages which isequal to the number of pulses in the series of any one of said It clockswhich occur during any one complete television scan line, means forloading the first stage of each of the n shift registers of said first 1television scan line delay logic means with the output of thecorresponding one of the u shift registers of said first-mentioned set,and means for applying as shift pulses to each respective one of said nshift registers of said second set of both said first and second 1television scan line delay logic means a preselected one of said Itclocks which is different from the clock applied as shift pulses to thecorresponding one of the first-mentioned set of n shift registers, butwhich results in the respective outputs from the corresponding shiftregisters of said first-mentioned set and said second set of both saidfirst and second serially connected 1 television scan line delay logicmeans all being simultaneously present during the occurrence of thesampling of the respective outputs of these corresponding shiftregisters by said 12 for combining said first, second and third outputdot samples, each of said others of said first set and all of saidsecond set, an AND gate having the output of said OR gate applied as afirst input thereto, and an inverter for applying said given particularone of said first set of outputs as a second input to said AND gate, theoutput from said AND gate constituting said edge key video signal.

1. In a digital generator of graphic symbols with edging for display ona display device exhibiting a television raster scan, said generatorbeing of the type which includes a character generator memory responsiveto the application thereto of a first multibit symbol code and a secondmultibit scan line per symbol height code for deriving an m bit paralleldot pattern manifesting a selected scan-line portion of a selectedsymbol to be displayed; the improvement therein comprising: a. a set ofn shift registers each having k stages, wherein both n and k are pluralintegers and m is equal to the produce of n times k; b. means forloading said k stages of each ordinal one of said n shift registers withthe i, n+i, 2n+i, . . . m-n+i ordinal ones of said m bits, where i isthe ordinal value of that ordinal one of said n shift registers; c.means for applying as shift pulses to each respective one of said nshift registers a corresponding one of a set of n clocks, each of said nclocks consisting of a series of pulses each having a duration of twhich occur at a repetition frequency substantially equal to 1/nt, andeach ordinal one of said set of n clocks being phase delayed by a timeinterval substantially equal to t with respect to the preceding one ofsaid set of n clocks, to thereby produce a set of respective outputs ofsaid n shift registers each pulse of which has a duration substantiallyequal to nt, d. first and second serially connected 1 television scanline delay logic means having the set of respective outputs of said nshift registers applied as respective inputs to said first line delaylogic means for producing a first set of corresponding outputs from saidfirst line delay logic means and a second set of corresponding outputsfrom said second line delay logic means, e. video dots shaping andphasing flip flops having said set of respective outputs of said n shiftregisters applied as first inputs thereto, said first set ofcorresponding outputs applied as second inputs thereto, said second setof corresponding outputs applied as third inputs thereto, and said setof n clocks as fourth inputs thereto for sampling all of each separategroup of corresponding ones of said first, second and third inputs witha different respective predetermined one of said set of n clocks,whereby said video dots shaping and phasing flip flops derives first,second and third output dot samples corresponding respectively to saidfirst, second and third inputs thereto, with each dot sample having aduration t; f. first and second serially connected dot delay logicmeans, each of which provides a delay substantially equal to apredetermined integral multiple of t, said first, second and thirdoutput dot samples being applied as inputs to said first dot delay logicmeans for producing a first set of corresponding outputs from said firstdot delay logic means and a second set of corresponding outputs fromsaid second dot delay logic means, and g. output means including firstmeans responsive to the presence of that given particular one of saidfirst set of outputs fRom said first dot delay logic corresponding tosaid second output dot samples for deriving a monochrome video signal,and second means responsive to the absence of said given particular oneof said first set together with the presence of at least another of saidfirst set, any of said first, second and third output dot samples, orany of said second set of corresponding outputs from said second dotdelay logic means for deriving an edge key video signal.
 2. Thegenerator defined in claim 1, wherein m is 32, n is four, k is eight,and t is 50 nanoseconds, whereby 1/nt is five megahertz and nt is 200nanoseconds.
 3. The generator defined in claim 2, wherein said graphicsymbols are for display on a display device exhibiting a televisionraster scan for a frame consisting of two interlaced raster-scan fields,and wherein said predetermined integral multiple of t is two, wherebyeach of said first and second dot delay logic means provides a delay ofone-hundred nanoseconds.
 4. The generator defined in claim 1, whereineach of said first and second serially connected 1 television scan linedelay logic means includes a second set of n shift registersindividually corresponding to each of the n shift registers of saidfirst-mentioned set, each of said second set of n shift registers havinga given number of stages which is equal to the number of pulses in theseries of any one of said n clocks which occur during any one completetelevision scan line, means for loading the first stage of each of the nshift registers of said first 1 television scan line delay logic meanswith the output of the corresponding one of the n shift registers ofsaid first-mentioned set, and means for applying as shift pulses to eachrespective one of said n shift registers of said second set of both saidfirst and second 1 television scan line delay logic means a preselectedone of said n clocks which is different from the clock applied as shiftpulses to the corresponding one of the first-mentioned set of n shiftregisters, but which results in the respective outputs from thecorresponding shift registers of said first-mentioned set and saidsecond set of both said first and second serially connected 1 televisionscan line delay logic means all being simultaneously present during theoccurrence of the sampling of the respective outputs of thesecorresponding shift registers by said different respective predeterminedones of said set of n clocks in said video dots shaping and phasingflip-flops.
 5. The generator defined in claim 1, wherein said firstmeans of said output means comprises a signal mixer for mixing saidgiven particular one of said first set of outputs with television syncsignals and television blanking signals.
 6. The generator defined inclaim 1, wherein said second means of said output means comprises an ORgate for combining said first, second and third output dot samples, eachof said others of said first set and all of said second set, an AND gatehaving the output of said OR gate applied as a first input thereto, andan inverter for applying said given particular one of said first set ofoutputs as a second input to said AND gate, the output from said ANDgate constituting said edge key video signal.